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Yosys can produce EDIF but not read EDIF. It would be nice if EDIF reading support was added to Yosys.
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OpenSUSE is a linux distribution used in the wild, so it would be good if we could provide release binaries for it as well.
(context: https://groups.google.com/g/verible-users/c/Z-iTXOakQUY )
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Could you please add MMCM to the Zynq7 parts? That's half the PLLs on the device, and the more accurate ones, at that. I'd try to do it myself, given that it appears to be nothing more than copying …
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Using the Surelog parser, built in gates (and, or, not, xor etc.) cannot take multi bit signals as inputs or outputs. If a multi-bit signal is used (e.g. sw[5]) it will default to the first bit instea…
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SYMBIFLOW-CLASSROOM-PROJECT
Using Yosys front end.
The following code does NOT initialize the memory:
// Load the Instruction Memory
if (TEXT_MEMORY_FILENAME == "") begin
$display("*…
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Some of the packages currently requires conda-forge:
https://github.com/hdl/conda-eda/search?q=conda-forge&type=
Which might cause glibc issues when installed on top of regular anaconda base envir…
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I'm trying to find the detailed information about the delays of some components or their library files in the 'report_timing.setup.rpt' file provided by OpenFPGA. Where can I find them?
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I use the latest uhdm to run this orv64 code and encounter segementation fault without more information
```
module top …
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It would be great for the Yosys version in YoWASP to have better SystemVerilog support through the usage of the Surelog+UHDM plugin. What would be the steps for making such a thing happen? Do plugins …