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Hello,
I'm having an issue or misunderstanding for communicating with the processor via UART. I downloaded the bitstream v8.0 into the ML605 board using iSE Impact, opened the UART channel on my co…
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https://forum.m-labs.hk/d/503-connectionreseterror-with-fresh-gateware
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I'm designing FMC carrier board for DI/OT project for CERN. The specification is [here](https://ohwr.org/project/diot/wikis/diot-fmc-carrier). Basically it's a board in the same ecosystem as the [syst…
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Sorry to ask this kind of basic questions.. I am a newbie in FPGA, so I do not know a lot of FPGAs. As you mentioned in the previous issue, kc705 fan activates their fan automatically. I am also curio…
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Hello,
I was able to build properly for the kc705 board for the Linux on vexriscv project but was unable to load the bitstream by running the command:
./make.py --board=kc705 --cpu-count=4 --loa…
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Hi.
I added your GMII & UDP stack like the KC705 example.
when I connecting the Ethernet cable from the FPGA to the PC, there is not a lot of traffic, {~1packet / 1sec on average},
I make ARP bro…
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# Bug Report
## One-Line Summary
Applets do not work and the dashboard raises a similar error at startup.
@sbourdeauducq , I expect this to be caused by the recent change to nixpkgs 20.…
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Win10 xilinx 2022.1, When I run 'make xsa' command I get the following error:
>>kria-vitis-platforms\kv260\platforms\vivado\kv260_vcuDecode_vmixDP>make xsa
/bin/vivado -mode batch -notrace -source…
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# Bug Report
## One-Line Summary
@sbourdeauducq , maybe I am having a misunderstanding, but the timing model of the `parallel` statement might be fundamentally off.
## Issue Details
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@gkasprow @sbourdeauducq @hartytp and whoever else is interested
I'm not fully aware of what the current state of Kasli-SoC is beyond what I can tell from the repositories. We are being asked regul…