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thanks a lot for this extension and the tutorials around the tang nano 9k ! its been super helpful getting started with fpga stuff for me.
im now trying to program a [icesugar-nano](https://github.…
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### Version
Yosys 0.40 (git sha1 a1bb0255d65, g++ 13.2.0-13 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
Synthesize a non-trivial design for the GateMate FPGA using de…
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Moving my notes here from [openXC7-snap #4](https://github.com/openXC7/openXC7-snap/issues/4) as the following has nothing to do with the snap.
After losing to the 60GB Vivado monster on my WSL dri…
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Using the attached json file, running nextpnr like so:
nextpnr-ecp5 --json top.json --basecfg /usr/local/share/trellis/misc/basecfgs/empty_lfe5um-45f.config --textcfg top_out.config --um-45k --…
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Hello,
I've a lot of issues with the SRAM example with the io constraints like `sram_addr_to_pad` not known.
When I try to change it to `ADR` in the file `sram_io_ice40`, I've got an error:
`ch…
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Not as-is since at least the constraints would need to be changed as this is for the Tang Nano 9K. But most of them should be pretty straight forward to port.
For example is there a spe…
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See https://github.com/gatecat/nextpnr/commit/6fc050a622e05bd9b484e4302d0ca0199e39a1fb
`TPKREG1`, for example, actually seems to configure `FFT0`. I'm not sure if this is bad naming from Quartus or…
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I'm have added code in bbaexport.py to write clock region data to the .bba file, and thereafter, it is converted into .bin file. Then, it can be loaded as memory-mapped-file in Nextpnr.
However, when…
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The following steps are similar to those outlined in https://github.com/kintex-chatter/xc7k325t-blinky-nextpnr/blob/main/README.md. I repeat them explicitly below, since there have been different erro…
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Building the example design for Icebrekaer from this repo https://github.com/Wren6991/SmolDVI, but using `-abc 9 -device u` as options to yosys, I see nextpnr hang on maybe 20% of runs.
This is a r…