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**Describe the problem/limitation you think should be addressed**
Inability to view an entire register as a vector during the design verification process with tools such as Verdi, SimVision etc...
S…
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### Description
Ensure V2(S) signoff criteria are still maintained (this is not a focus area block).
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### Description
Ensure D2S signoff criteria are fulfilled after focus area changes have landed.
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I issued the following pull requests:
https://github.com/openhwgroup/core-v-verif/pull/1220
https://github.com/openhwgroup/core-v-verif/pull/1221
They are to make core-v-verif compile after cha…
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Hi,
There is one included file in "src/doe/rtl/doe_reg_uvm.sv": doe_reg_covergroups.svh
But it is not in the release, is it missed ?
Best Regards
Derek Wang
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### 1. Issue or feature description
```OutOfnvidia.com/gpu``` error appeared when node is restarted in the GCE with https://github.com/NVIDIA/k8s-device-plugin after `Instance terminated during mai…
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PeakRDL tool generates uvm register model not correctly. For all registers, the volatile field is always 1, it doesn't matter if I write in ip-xact volatile true or false. The tool ignores this field.…
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Hi,
I'm using the rggen generated models for our design and verification.
And I'm using AXI interface, for which I'm using AXI VIP for verification. when I'm trying to start uvm_reg_access_seq I'…
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I never had this warning from dmesg before.
[14364.568530] hwmon1: Concurrent access to the ACPI EC detected. Race condition possible.
Started upon installing kernel 6.4.2 from t…
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gn223 updated
11 months ago