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### Hierarchy of regression failure
Chip Level
### Failure Description
UVM_ERROR @ 3383.073776 us: (cip_base_scoreboard.sv:436) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_er…
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### Hierarchy of regression failure
Chip Level
### Failure Description
Offending '(dft_jtag_i == '0)' has 1 failures:
Test chip_tap_straps_prod has 1 failures.
4.chip_tap_straps_prod.3522213289…
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### Hierarchy of regression failure
Chip Level
### Failure Description
UVM_ERROR @ 4600.294014 us: (sw_logger_if.sv:521) [otbn_mem_scramble_test_prog_sim_dv(sw/device/tests/otbn_mem_scramble_test…
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CC: @a-will @alphan @arunthomas
Last week, I observed an issue with JTAG-based ROM e2e tests like [:sram_program_fpga_cw310_test_otp_dev](https://cs.opensource.google/opentitan/opentitan/+/master:s…
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### Hierarchy of regression failure
Chip Level
### Failure Description
Offending '(dmem_rdata_bus == 'b0)'
UVM_ERROR @ 9128.296472 us: (otbn.sv:1217) [ASSERT FAILED] NonIdleDmemReadsZero_A…
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### Hierarchy of regression failure
Chip Level
### Failure Description
UVM_ERROR @ * us: (prim_reg_cdc_arb.sv:248) [ASSERT FAILED] ReqTimeout_A has 1 failures:
Test chip_sw_ast_clk_outputs has 1…
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The top_earlgrey XBAR block level as well as the full chip level use the generated `xbar_*_bind` SV files which bind the `tlul_assert` instances to all hosts and devices.
The associated fusesoc co…
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### Hierarchy of regression failure
Chip Level
### Failure Description
UVM_ERROR @ 3935.230296 us: (chip_base_vseq.sv:159) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chi…
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### Hierarchy of regression failure
Block level
### Failure Description
```
User terminated with CTRL-C has 1582 failures:
Test aes_wake_up has 1 failures.
0.aes_wake_up.2856553756
Log /conta…
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### Hierarchy of regression failure
Chip Level
### Failure Description
UVM_FATAL @ * us: (mem_bkdr_util.sv:480) [mem_bkdr_util[Rom]] file test_rom_sim_dv.scr.*.vmem could not be opened for r mode h…