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It protects thread_info from corruption in the case of stack overflows.
Its address is harder to determine if stack addresses are leaked, making a number of attacks more difficult.
See arm64 commi…
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If one core supports only imc ( -march=rv32imc), what is the best way to disable other ISA groups?
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Consider supporting Kendryte K210?
Relevant information:
https://kendryte.com/
https://forum.kendryte.com/category/5/ide
https://forum.kendryte.com/topic/8/k210-windows-flasher-k-flash-v0-3-0-rele…
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```
Build Configuration:
BB_VERSION = "1.40.0"
BUILD_SYS = "x86_64-linux"
NATIVELSBSTRING = "universal"
TARGET_SYS = "riscv32-oe-linux"
MACHINE =…
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Big board, big FPGA, plenty of pins and PCB space.
DDR3 is great but some for some low-latency application SDRAM is still better.
Can you see if possible to add a 32-bit 64MB SDRAM on the next relea…
emard updated
5 years ago
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I want to handle timer interrupt. To do it, I should set `mtimecmp` firstly. But I have read [riscv-privileged-v1.10](https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.…
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Questions from Alibaba.
1.
Normally, RV64 treats 32-bit data as signed data. This means that when 32 bits are involved in the arithmetic, MSBs are always sign extended to 64 bits. However, this is a…
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riscv-testsをロードしたいので、elf loaderを作ろう。
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Hi,
I've got an issue while trying to execute a code compiled by *riscv64-unknown-elf-gcc-8.2.0-2019.02.0-x86_64-linux-centos6* (from https://www.sifive.com/boards/) on the *ibex* core.
Listing:
…
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So I've been banging my head on the desk trying to understand the debug/jtag. I think the problem is related to reset.
For reference, this is my qsys diagram:
![qsys](https://user-images.githubu…