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Version: 9.3
GCC 11.2.1, Python 3.8, SWIG 4.0.2
**What did you do?**
cmake ... -DBUILD_PYTHON:BOOL=ON
make
**What did you expect to see**
build succeeds
**What did you see instead?**
`…
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Hi,
Sorry for for the generic title, but this morning, after switching on my icicle kit I found it to be stuck into a weird state. Nothing is output from the UARTs, and the eFP6 is not recognized b…
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Hi!
Sorry to bother you again, but it seems that I cannot make another one of my ICICLE Kit pass the DDR training. I am using main branch of the BsP.
To enable LPDDR4 support, I just added the #…
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When building a litex soc with microwatt, the following toolchain works fine for a simulation:
```
powerpc64le-linux-gnu-gcc (Debian 11.2.0-9) 11.2.0
```
```
litex_sim --cpu-type=microwatt --cpu-…
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Hello,
I'm having a problem with etherbone: the connection stops working if two packets are sent too close to each other.
The only way to restore connection is to power cycle the board.
The packets…
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As described [here](https://github.com/pulp-platform/pulpissimo/blob/master/boot/README.md) PULPissimo have several capabilities for running boot process.
JTAG boot and QSPI boot are quite straight-f…
iDoka updated
2 years ago
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- [x] Disclose initial draft of the methodology and discuss with WG
- [x] Hardware acceleration across silicon architectures (comparing results across _somewhat_ equivalent commercial solutions) http…
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Hi,
I followed all steps till
$ cd vsim
$ make
Here I could n't go ahead due to not having bought synopsys vcs licence.
My question is, even without vcs, are all generated verilog complete?…
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Loading the design via indirect JTAG into nonvolatile memory with Vivado requires basically the same steps as loading it into volatile configuration memory, the main difference is that the configurati…
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By exposing the dmi signals instead of the JTAG signals, it's possible to create target-specific transports for devices without accessible JTAG signals. Primarily, this would allow using FPGA macros s…
olofk updated
2 years ago