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Hi, I'm a student interested in FPGA and want to learn more about SDR, especially AD936X based ones. I wonder if it's possible to have AD936X extension boards for low-cost FPGA platforms like the PYNQ…
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Hello,
I'm currently trying to compile the bit stream for arty a7 35t fpga in the Linux-on-litex-vexriscv project from enjoy digital.
Here is the link for this project: https://github.com/litex…
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```bash
(litexenv) :~/litex_install/litex-boards$ python -m litex_boards.targets.digilent_arty_z7 --build --load
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INF…
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Hello,
I have a problem to generate the preloader with the DE0_Nano_Soc.
The configuration is the following:
Quartus Lite 18.01 and DS5 standard edition V18.01 on Windows 10,
I followed the proce…
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Dear Sir:
Does any have the vexriscv smp boot up fail problem. the code base which newer than 2021 0401 seems boot up failed if CPU counts > 1.
If setting cpus counts to 1 , the boot up is very …
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Sometimes when starting Jackd channel 1 becomes channel 7, sound moves form the fisrt rca jack to the seventh one. This occurs roughly 1 time out of 10. Restarting Jackd returns channel 1 to rca 1.
I…
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Hi.
I saw your interesting projects on the Innova2 - and wanted to ask you:
Have you used the Innova2 FPGA to control the network chip's (ConnectX-5) ingress/egress packets?
I want to hack some…
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I need support for Project Mistral for my chameleon96 and Terasic Sockit Altera Cyclone V boards
A blinky example done with project mistral is done here https://github.com/kprasadvnsi/mistral-CV96-bl…
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# Prerequisites
Please answer the following questions for yourself before submitting an issue.
- [ ] I am running the latest code. Development is very rapid so there are no tagged versions as of…
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I am learning really well through the project wiki. Thank you so much.
However, I have some questions that are not solved.
When a module is extracted from the Phantom 4 Pro (wm331) firmware, 21 …