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Hi,
Thanks a lot for releasing the netlists for this dataset. I tried to write a parser, but have been facing issues getting the same performance. Would you be able to release your parser to conver…
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```console
Stack dump:
0. Program arguments: /usr/bin/clang++-10 -DDEBUG -DEESCHEMA -DGLM_FORCE_CTOR_INIT -DHAVE_STDINT_H -DKICAD_CONFIG_DIR=kicad -DKICAD_SCRIPTING_WXPYTHON -DKICAD_SIGNAL_INTEGRITY…
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Hi,
I am using Verilog-perl as a lint. Is there any option to suppress the include file error such as:
%Error: ###.sv:##: Cannot open ###.svh
Stopped at .../Verilog/Parser.pm line 186.
than…
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It would be nice to write a script that leverages vivado to ensure that composed netlists are parse-able with vivado. Currently this would have to be manually run.
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This was done by following the example on http://yosyshq.net/yosys/screenshots.html precisely.
```
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yosys> abc -liberty cmos_cells.lib
13. Executing ABC pass (technology mapping using ABC).
…
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can someone please help me out to remove this error???
sorry for the log file I can't find it. so I pasted the entire error message after make command.
hope you can find it.
cking for ca…
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The following little script consume very much memory very fast due to a broken netlist. The netlist is parsed successfully but the attempt to display it seems to run into an infinite recursion.
(The …
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您好!我想使用你们开发的iEDA工具,但通过yosys生成的Netlist文件和sky130中的gcd.v文件格式不一致,调用iEDA命令运行会对always和assign语句报错,请问是有一些特殊的生成设置吗?
![image](https://github.com/OSCC-Project/iEDA/assets/103937567/fdadbdcd-5aad-4786-8647-636d0…
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May be related to #21 .
Using the base files for both Lucid and Verilog projects, `Build Project` fails:
```
Starting iceCube2...
C:\Program Files\Alchitry\Alchitry Labs>SET TCL_LIBRARY=C:\…
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The goal of UHDM is to allow "users" (like Yosys, Verilator and Icarus) of a SystemVerilog parsers not to care about the exact parser implementation. However, currently the only parser which exposes t…