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Pcie is useful in various domain in fpga. However, there is not any facility to use pcie dma in SpinalHDL.
I'm currently working on it. Firstly, I will focus on ultrascale device, I will mainly bo…
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Hi,
when I use these parameters "--xlen 64 --with-mul --with-div --with-rva --with-rvZb --with-boot-mem-init --reset-vector 0x0 --physical-width 32" to generate the VexiiRisc.v, the FetchCacheles…
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Publishing a docker image of Spinal & tools might be interesting to make it easier for projects using SpinalHDL to build their CI workflows. I also think it would bring more flexibility, ease caching …
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I realized that Altera allows users to write sdc constraints inline with Verilog, which inspired me that is it possible to generate IP related constraint files by adding new syntax in SpinalHDL, the o…
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Hi,
I found out a few things about ["modified" Briey SoC](https://github.com/jmio/ECP5_Brieysoc/tree/dev) not working on the actual device (ECP5, ICESugarPro).
For "non-booting" FPGAs with dev-…
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The documentation seems to be way behind the SpinalHDL lib repository.
As an example, the lib has AXI4 Crossbar, which is never mentioned in the documentation. A lot of the com modules are not docu…
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Is there a reason why slicing of `Vec`s are not implemented yet?
I'm adding that functionality using an implicit class to `Vec`:
```scala
def apply(range: Range): Vec[T] = Vec(for (i
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The EU has €270 million in funds for Risc-V projects.
https://www.hpcwire.com/2022/12/16/europe-to-dish-out-e270-million-to-build-risc-v-hardware-and-software/
We should figure out how to get …
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At the VexRiscv commit used by pythondata-cpu-vexriscv to build the verilogs, there is a clash in the use of CSR 0xBC0, used both by CfuPlugin for its state/index/enable register, and by the external …
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I think should have a general Verilator Emitter to unify "chisel-tester", "chisel-tester2", "chiselTests", "firrtlTests", "rocket-chip emulator", "hardfloat FMA tests", and other possible emulators to…