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https://reference.digilentinc.com/reference/programmable-logic/arty-a7/arty_a7_100_risc_v/start
I am trying to implement the above link to learn about RISC-V. However when I try ./build.sh I get a …
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Hello,
First of all, thanks for your tutorial, it's great and easy to follow.
I followed it using an Arty 100 instead of the Arty 35 and everything seemed to work fine. However, when I try to run th…
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Hello everyone,
I am interested in creating a SoC with 2 cores and a custom communication between them (UART or something else). But reading the BaseSoC implementation, I see no trick that I could …
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I want to change the MEMORY_SIZE size from 8192 bytes to 1024 bytes to fit my FPGA board (my board is FPGA DE-2 KIT). I changed the MEMORY_SIZE from the hex file to 1024 bytes and also the Verilog cod…
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Hello,
I have been attempting to build the core for the Arty-A7 100T. I did get it to build but I wanted to point something out and also would like some guidance for getting CHERIot compiled softwa…
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I tried to build the core following the instructions in the `build` directory, but it failed with the following error:
```
INFO: [Synth 8-6155] done synthesizing module 'ibex_top' (0#1) [/home/xxxxx…
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Hey :)
We want to connect an external button to an Arty A7 and develop a small IoT application.
We identified the following steps to be crucial for a successful connection:
1. Add the location …
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Hello,
I was checking out the repository to see how to use Linux and Multizone on the same board, and I noticed that it only supports the HiFive Unleashed board, which is now discontinued. I am curre…
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Do you plan to support other FPGA boards in addition to the current Genesys 2?
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### IDLE (arvalid always low)
![lpddr_idle](https://github.com/user-attachments/assets/44298f5c-6b50-4ad0-aad4-de4cc4b63668)
[lpddr_idle.vcd.zip](https://github.com/user-attachments/files/163652…