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See #34 - also LiteX/VexRiscv but this time with Debian. This means more advanced capabilities, and the tutorial should showcase some of those to make the user understand how to build a useful, demo-w…
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There is a MCU in the RV1106. Is there a way to leverage it?
Like SG2002, the big core runs Linux, the small core runs RTOS, and can load code to the 300Mhz 8051 MCU inside.
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**Describe your proposed improvement and the problem it solves.**
Build releases for Linux/RISC-V (64-bit).
**Describe alternatives you've considered.**
\- (There is none)
Related to:
*…
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[rv8](https://github.com/michaeljclark/rv8) demonstrates how RISC-V instruction emulation can benefit from JIT compilation and aggressive optimizations. However, it is dedicated to x86-64 and hard to …
jserv updated
11 months ago
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Does the current version support the vector extension?
I try running this:
riscv64-unknown-elf-gcc main.c asm_func.s -o ./a.out -march=rv64gcv
and getting this:
Assembler messages:
Error:…
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Hi!
I have a question about compiling programs for 32-bit cores. I tried to use Verilator to test Bare Metal RISC-V Programs with TinyCore( Is it 32-bit core, right?). First of all, I make TinyRoc…
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The readme recommends, https://www.sifive.com/software/ "Prebuilt RISC‑V GCC Toolchain and Emulator" as the path to download the gcc toolchain.
The text no longer exists on that page. All the links o…
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I am running riscv-arch-test to validate an emulator I am writing.
sails logs this of `cjal-01.S`:
```
mem[X,0x80000180] -> 0xA029
[101] [M]: 0x80000180 (0xA029) c.j 0x5
mem[X,0x8000018A] -> 0…