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I am hitting below error while running example design,
[INFO][FLOW] Using platform directory ./platforms/nangate45
/bin/sh: 0: Illegal option -o pipefail
/bin/sh: 0: Illegal option -o pipefail
/…
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@gezalore
Running the extended tests on develop-v5 branch, and updating that branch's verilator submodule to develop-v5 HEAD fails.
```
%Warning-DEPRECATED: /svaha/wsnyder/SandBox/homecvs/v4/v…
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Hi all,
I am trying to install the RISC-V GNU toolchain in order to compile for [WD SweRV-EL2 core](https://github.com/chipsalliance/Cores-SweRV-EL2).
I followed the guidelines to install the to…
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The core is trying to include files that don't exist in the design. For example:
```
error: no such file or directory: '/root/sv-tests/sv-tests/build/chipsalliance.org_cores_SweRV_EH1_1.8/sim-verila…
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Although I can't find documentation stating this, it seems that any implementation of `pub` traits will not be optimsied out in the final binary.
A good example of this is the `print_full_process()…
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Hi, @jrahmeh @aprnath @olofk
I would like to know if anybody has run compliance on EL2.
I am currently running compliance (branch 1.0) on EL2 for "I" instructions. I am having an issue that when th…
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Hi all,
I am trying to install the RISC-V GNU toolchain from source in order to test this core.
I followed the guidelines to install the toolchain ([2022.03.25 version](https://github.com/riscv-…
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When I run the following command in the root of the repository:
`fusesoc --cores-root . run --target=sim chipsalliance.org:cores:SweRV_EH1:1.8`
I get the error:
```
ERROR: Setup failed : Cannot fi…
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Hello i want to know does the feature of Machine timer interrupt is enable in the new branch of SweRV El2. As previously i got a response that
**timer_int input is not configurable and causes anothe…
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Hi,
I am currently trying to run the RISCV compliance tests in [https://github.com/riscv/riscv-compliance](https://github.com/riscv/riscv-compliance) on the EH2 core using a tool named Riscof ([htt…