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In multiple source files, a conditional signal assignment statement is used within a process, which is illegal in VHDL-2008. Instead an if statement or case statement should be used.
During compila…
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The following code :
```python
from myhdl import block, Signal, always
@block
def flipflop(s, r, q):
@always(s.negedge, r.negedge)
def proc():
if s == 0:
q.next =…
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Hi everyone, I would like to write a small tool which, given a VHDL file describing an entity plus its architecture, would allow me to draw its corresponding schematic. It should at least include:
…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
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Hi Alex,
while working on [Corundum Issue 122](https://github.com/corundum/corundum/issues/122), we (foremost @sessl3r, @andreasbraun90) have done a quick and dirty simulation of the `axis_fifo.v` …
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Respected Sir
I am trying to take the necessary design files and the testbench files [sv files] to run on Xilinx Vivado , but couldn't map onto which are all the files typically needed.
I am re…
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If I perform the following steps, everything builds ok using trellis, and I get the BIOS prompt.
```
cd litex-boards/litex_boards/targets
./radiona_ulx3s.py --build --device=LFE5U-85F --cpu-type=ve…
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I have a C application that allocates some memory space. Then, GHDL is started inside the application, so the allocated space is available to the simulation. In the testbench, I execute `buffer.init()…
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**Description**
I have a VHDL2008 testbench with VUnit that includes a module from the Xilinx UNIMACR/UNISIM library. I managed to sucessfully compile the Xilinx libraries using the [script from the …