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there are some warning below.
1. WARNING: [VPL 17-301] Failed to get a license for 'ap_opencl'. Explanation: The license feature ap_opencl could not be found.
2. WARNING: [VPL 60-1142] Unabled to re…
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hello i'm new to using docker i'v downloaded the without vivado version and now i want access vivado in my host machine to synthesis the code !!!! is it possible ? i mean how should we change this lin…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Ok so basically, I need to use CVA6 to add a peripheral to it. For that I want to open …
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Hi! I meet some problems.
**WARNING: [HLS 200-885] Unable to schedule 'load' operation ('__Val2__') on array 'buffer_data_V' due to limited memory ports. Please consider using a memory core with mo…
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Hi wady101
I cannot build the project using the setup script. I am using PYNQ 2.5 (from tag) and Vivado 2019.1 .
This is the error:
```
ERROR: [BD 41-79] Exec TCL: Specified object '/adau1761_0'…
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Add the ability to separate out generated code by namespaces. So spirit:version creates a Version class in a Spirit namespace and xilinx:version creates a different Version class in the Xilinx namespa…
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I think I've encountered a bug that affects the pin mapping for the Basys3 board (part name xc7a35tcpg236-1). I've got a program that maps the 16 switches to a seven segment display but the behavior o…
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Hi,
I'm working on the PyTorch ResNet50 model, I'm using the Vitis-ai 2.5 version, KV260 platform with Petalinux 2022.1, DPU IP v4 (Vivado flow)
I compiled the ResNet50 model for 1 core B4096 …
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**Environment**
- OS: Ubuntu 20.04.5 LTS
- Vitis version: 2021.1
- Platform: [xilinx_u280_xdma_201920_3]
- TAPA version: 0.0.20220807.1
 with newest version of RFNOC after having applied your patch to uhd-fpga. However the design does not synthesize.
I believe that the changes…