-
icetime can't parse new pcf options such as `-nowarn`, `-pullup`, and `-pullup-resistor`. It fails with the message:
```
// Reading input .pcf file..
icetime: icetime.cc:230: void read_pcf(const …
-
Currently SDC constraints are passed directly to VPR, which means the net names need to be the output net names from Yosys. However, constraints should be specified on the nets in the input verilog, …
-
The target is to be able to measure the performance of various routing algorithms done with the help of RapidWright.
However, first we need to integrate RW with the fpga-tool-perf.
-
I wonder if nextpnr has a way to put constraints on I/O-timing. In Quartus, there's set_input_delay and set_output_delay (I found http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/ to b…
-
It seems to never end:
```
Info: iter=20608 wires=8032 overused=1 overuse=1 archfail=NA
Info: iter=20609 wires=8032 overused=1 overuse=1 archfail=NA
Info: iter=20610 wires=8032 overuse…
-
The `.bat` file generated on Windows is invalid. Contents of the file are:
```
@echo off
rem Autogenerated by LiteX / git: cb85a8ca
yosys -l colorlight_5a_75e.rpt colorlight_5a_75e.ys
|| exit …
-
I can start the GUI with a json and pcf specified on the command line:
```
nextpnr-nexus --json hps_proto2_platform.json --pdc hps_proto2_platform.pdc --fasm hps_proto2_platform.fasm --device LIFCL-…
-
# Version:
nextpnr-ice40 -- Next Generation Place and Route (git sha1 2898d81)
# Input:
```verilog
// look in pins.pcf for all the pin names on the TinyFPGA BX board
module top (
i…
BigET updated
4 years ago
-
I have a design that fails initial placement. This is mostly because of incompatible CE lines for the flipflops and it is for a LP384 which doesn't have a lot of resources and I'm trying to pack 330 L…
-
For the design I am working on, targetting Crosslink-NX17 (nexus family), the latest master branch of yosys (commit 08c319fc352fb2670b7416b5fb16ddcb9a400049) produces a bitstream that seems to be reje…