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### Description
I wanted to write down some information that I got when running megaboom through Quartus and I'm filing this as a feature request. We can mark this issue as "help wanted" or perhaps c…
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File "/home/staff/elesamj/sky130a/opennvram-reram-main/compiler/options.py", line 207, in set_temp_folder
default_openram_temp = os.path.join(os.environ['SCRATCH'], 'openram')
File "/usr/lib/…
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**Describe the bug**
I have generated a SRAM whose size is 16 Row * 512 bit,the area is 0.35 mm^2 (using freePDK-45nm).
However, I generated the same size of SRAM in CACTI, the area is only 0.028 mm…
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Hi,
How have you created the instances of reram using OpenRAM?
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We are trying to use conda environment for the tools used by OpenRAM. I have a recipe for klayout (which I got from [conda-eda](https://github.com/hdl/conda-eda/tree/master/misc/klayout) and modified)…
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Hi,
I see in file [/OpenRAM/macros/configs/example_config/freepdk45.py,](https://github.com/VLSIDA/OpenRAM/blob/stable/macros/configs/example_config_freepdk45.py) there's definition on slew_scales …
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I noted the sky130 dont have gds files. then how is modified reram open ram is compiling all elements?
![image](https://user-images.githubusercontent.com/30805083/230722165-589198da-763d-46b0-8f06-f5…
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### Description
FPGA designs can have inferred SRAM. Inferred SRAM is supported by Yosys, but if it is inferred it is automatically converted to DFF, which makes the designs explode in size and time.…
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I am setting an obstruction over openram so it can be routed to without causing DRC errors.
```
set ::env(GLB_RT_OBS) "li1 0 0 2920 3520,
met1 344.0 475.5 823.78 873.0,
m…
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Hi, I'm a student at USC, and I'm working with a professor on a project where we were hoping to utilize OpenRAM. I see that you have guidelines for what might be required to port OpenRAM to a new tech…