-
Tried your latest panog1 to play with usb - got some life after removing old MIF includes in pick ROM and RAM modules - but running into HALT on USB. Was wondering if a) you have similar issues and b)…
-
as noted in https://github.com/gojimmypi/VerilogLanguageExtension/issues/21#issuecomment-620237275 - performance on large files is really poor due to excessive re-parsing of the entire buffer,
-
Hi! While playing around with `do_fuzzdesign.py` for the cva6-c1 CPU, I have noticed three program descriptors whose "bug" correspongs to `list index out of range`. The descriptors in question are as …
-
Dear Bruno,
my congratulations for squeezing a RV32I core into the Icestick !
I read your Verilog files with joy and I wish to share an idea on how to save a few more LUTs for more peripherals: …
-
There is a target "check" that has "check-yices" as dependency. But that does not exists. Is this a typo?
https://github.com/YosysHQ/picorv32/blob/336cfca6e5f1c08788348aadc46b3581b9a5d585/Makefile#…
-
Can anyone show an example of how to compile the tests code .s files with riscv64-unknown-elf-gcc.
-
HI, I am interested to learn PicoRV32, So Can you update Architecture & Pipeline, Datasheet for PicoRV32?
-
The current GCC build (I did not try Clang) for BIOS/firmware does not strip away unused symbols, resulting in large binaries (especially when adding dependencies).
I tried adding various flags in …
-
I'm currently exploring the possibility to create an ASIC from a specific NeoRV32 configuration. As I'm still a student without much experience in digital design I still have a lot of things to figure…
ucycg updated
4 months ago
-
### Subject
[Documentation] for documentation errors.
### Describe the bug
I'm currenlty running the Autotuner but have been impeded by this message. I didn't modify any script files either.
```…