-
### Example
```sv
module m (
input [1:0] i1,
i2,
output [3:0] o
);
assign o = i1 + i2;
endmodule
```
Compile using:
```sh
verilator --binary m.sv
```
### Current O…
-
This is a tracking issue for the first steps towards implementing a hardware description language for Tydi types.
Currently the Tydi crate provides modules with the logical and physical stream type…
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Hi,
I am trying to build the EL2 design for the Intel Cyclone 10 GX FPGA. This is using the free license within Quartus Prime Pro 21.2.
I am having issues with the `el2_param.vh `and `el2_pdef.vh`…
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The recent change definitely helped things, but the build is still not configured correctly. Most relevant slang error:
```
../../../third_party/cores/ariane/core/cache_subsystem/cva6_hpdcache_subsy…
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@LarsAsplund, @kraiger and @umarcor,
I would like to propose a broad strategy for co-simulation with VUnit. I really like what @umarcor has been working on, but I think his approach leaves most o…
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> Hi - can you please add support for SystemVerilog files (and maybe VHDL files too)? this is the main language we use
- from [jonnyboynewton](https://github.com/jonnyboynewton)
- [original issue]…
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In Clash `master` and `1.6`, there is a bug when generating HDL under very specific conditions. Only with GHC 9.0.2 (out of the versions we test in CI), with multiple hidden enabled, an annotation fro…
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See the unit test, the 2D (and higher array orders) work fine if the inner dimension is sliced e.g.
```python
register_array[0, :]
```
However, it does not work on the outer dimension
```pytho…
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Title says it all I think.
Reproducer:
```haskell
module Example.Project where
import Clash.Prelude
topEntity ::(BitVector 8)
topEntity = deepErrorX "broken"
```
compiled with `cabal r…
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**Note.** Before applying, make sure you can receive notifications from Github. Once you apply, make sure you're subsribed to receive emails when someone responds to the issue. We will respond to your…
gn223 updated
10 months ago