-
Hello,
[This discussion](https://sourceforge.net/p/ngspice/discussion/120973/thread/51228e0b01/) links to this repository. Further down, there is a zipfile that contains what is probably an ancest…
-
**Describe the bug**
When creating a project directory containing spaces, such as `/home/user/hal_projects/foo bar/`, executing a simulation using `netlist_simulator_controller` with the `verilator` …
-
**Description**
I am trying to build ghdl on CentOs 7 with gcc back-end. In the past I have successfully build ghdl on other systems.
Initially I tried with gcc source 11.3.0. Which failed. Next, …
-
For some types of LVS errors, `netgen` does not exit with `return code 1` and the temp-sense-gen still says that "LVS is clean!" when it is not.
For example:
![image](https://user-images.githubuse…
-
Datasheet field is a built in and needs special handling because it's stored differently.
-
### Description
When instantiating multiple macros via the Verilog `generate` statement the power connections are lost somewhere in the flow and thus the macros are not connected to power.
I had a…
-
While porting SVUnit to Verilator I stumbled upon a subtle issue. Function calls in SV are allowed without braces - (). Looks like Verilator does not like that style. Sample error:
```log
%Error: …
-
With latest OpenLane/OpenROAD `user_project_wrapper.def` unable to read and tool getting crashed with following message:
```
[STEP 4]
[INFO]: Running IO Placement...
[INFO]: Applying DEF templat…
-
#### Proposed Behaviour
We'd like to model multi-die stack FPGAs. This is needed for the crossroads project, and will likely be useful to others.
#### Current Behaviour
The sub_tile feature almos…
-
When I use spydrnet on a reversed-netlist, I get an error like this: `AssertionError: expected . to begin parameter mapping but got ) Line: 8619` I determined that it is because the reversed netlist g…