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I am using svlangserver in Neovim with the default settings.
The linter is Verilator 5.015.
In my projects, the linter emits this error message for all `import`s:
> Importing from missing packa…
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Hi is it possible to add a feature to this tool so it will ignore defines in VUnit testbenches?
See Example - https://vunit.github.io/user_guide.html#systemverilog-test-benches
It would also be…
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I am having difficulty making an SV enum public using the `verilator_config mechanism.
The enum is defined in a package:
```
package bbus_pkg;
typedef enum [1:0]
{
BBUS_CS_NI…
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In my design, there is a definition for macro function as shown below.
```
`define log2(VALUE) ((VALUE) < ( 1 ) ? 0 : (VALUE) < ( 2 ) ? 1 : (VALUE) < ( 4 ) ? 2 : (VALUE) < ( 8 ) ? 3 : (VALUE) < ( 16…
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SystemVerilog is a very popular hardware description language (HDL). Google is working on improving the ecosystem around this language, including developing linting and code fixing tooling. It would b…
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According to [web](https://docs.ctags.io/en/latest/man/ctags-lang-verilog.7.html),tagbar config need add other labels.
```
ctags --list-kinds-full=SystemVerilog
#LETTER NAME ENABLED REFONLY …
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I've been trying iverilog ("icarus verilog") on the system verilog code output from clash (approx 1.6.3) but it won't compile, well, parse, because .... iverilog doesn't seem to accept the repeat …
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identify all keys in the template file that follow those paterns:
- `{}`
- `{=}`
- `{{}}`
- `{{}}`
- `{{}}`
- `{{=}}`
- `{{=}}`
- `{{=}}`
example parterns:
- to create a list of all System…
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I found that in the reset logic of the **controller.sv** module, the assignment to the register array is done using a scalar value. However, this results in an error during compilation with Quartus II…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything rel…