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Summary
## System information
```
MyHDL Version: 0.11
Python Version: 3.6.9 ad 3.11.4
```
VHDL code generation works with python3.6 but not python3.11.
I have the following component in a f…
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i tried to change a python simulation in to a icarus-cosimulation. it seems to only work if i remove the **tb.config_sim(trace=True)** statement.
otherwise it says: _AttributeError: 'Cosimulation' ob…
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Hi, and I'm using PyMTL to design hardware where we need to generate different case statements according to the given arguments. I have searched for anything about "case" in the source code but I don'…
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The application generates this code:
```python
crcOut[0].next = crcIn[5] ^ crcIn[7] ^ crcIn[8] ^ crcIn[9] ^ data[5] ^ data[7] ^ data[8] ^ data[9]
```
but it must be:
```python
cr…
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Here I have some Verilog code
[error.zip](https://github.com/YosysHQ/yosys/files/2476242/error.zip)
and I am running yosys on it, but it gives an error
`ERROR: Missing edge-sensitive event for this…
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i have the question where i find the ./myhdl.vpi. do i have to build one from the myHDL-source directory and copy it in the python-directory?, or is it already somewhere installed? or should it be bui…
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myHDL is perfekt to simultate and generate verilog for FPGAs.
myHDL constants will be converted in the verilog code to numbers. this is not so nice, but works in most cases. But today i had problems…
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Hi,
I'm running the following python code:
```
from myhdl import block, instance, Signal, intbv, always_comb, delay
@block
def full_adder(a, b, cin, mysum, cout):
@always_comb
def …
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if i use an list of signals, its possible to set a few as logic, and the others as flip-flops. the generation of the reset if don't look what signal is set in the @allways_seq() procedure and sets he …
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**Is your feature request related to a problem? Please describe.**
I am debugging a system which obviously contains state-machines as *A State Machine is worth a thousand Equations*
GHDL does not e…