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**Describe the bug**
When creating a project directory containing spaces, such as `/home/user/hal_projects/foo bar/`, executing a simulation using `netlist_simulator_controller` with the `verilator` …
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**Description**
I am trying to build ghdl on CentOs 7 with gcc back-end. In the past I have successfully build ghdl on other systems.
Initially I tried with gcc source 11.3.0. Which failed. Next, …
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For some types of LVS errors, `netgen` does not exit with `return code 1` and the temp-sense-gen still says that "LVS is clean!" when it is not.
For example:
. Looks like Verilator does not like that style. Sample error:
```log
%Error: …
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With latest OpenLane/OpenROAD `user_project_wrapper.def` unable to read and tool getting crashed with following message:
```
[STEP 4]
[INFO]: Running IO Placement...
[INFO]: Applying DEF templat…
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#### Proposed Behaviour
We'd like to model multi-die stack FPGAs. This is needed for the crossroads project, and will likely be useful to others.
#### Current Behaviour
The sub_tile feature almos…
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When I use spydrnet on a reversed-netlist, I get an error like this: `AssertionError: expected . to begin parameter mapping but got ) Line: 8619` I determined that it is because the reversed netlist g…
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### Description
This is MPW CI design passed successfully with `2022.11.02` and fails with `2022.11.10` and above.
Between only `OpenROAD` commit got changed. Seems while reading [DEF](https://…