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@umarcor @LarsAsplund @JimLewis @eine @suzizecat @Paebbels @nfrancque I have been talking a bit with @qarlosalberto about potentially creating a sphinx builder/autodoc plugin for HDL, although I'm mor…
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I am trying to run the verification for the core. I have installed the toolchain as instructed. However, while trying to install and build spike simulator. I am seeing these issues. I have gone …
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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**Note: This is a DV/simulation-only clone of a SiVal test tracked in https://github.com/lowRISC/opentitan/issues/20635.**
### Test point
https://github.com/lowRISC/opentitan/blob/d161dede9cfb98…
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For a legal Verilog file:
`define A t;
module test`A
wire a;
wire b;
assign a = b;
endmodule
Verible parser rejects it with
test1.v: test1.v:2:12: syntax error, r…
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Dear Maintainers,
Thanks for providing svlint (and sv-parser). The following piece of example code should be valid systemverilog from my understanding (ignore that the functionality does not make sen…
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Verilator does not allow DPI-C imported tasks cannot pass simulation time, else they get deadlocked as per this issue: #4225, unlike other simulators (Vivado xsim...).
### My use case:
I am buildi…
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We have some projects that use recent Microsemi devices and they have stopped providing device libraries in VHDL.
As I understand the intention of the verilog support was to be able to simulate with …
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Hello!
I'm looking to adapt just the PPU code (ppu.sv and anything that it depends on) from this project to run on its own. It would run on a suitable FPGA chip with enough physical pins (>40) to r…