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- May help to prevent malware from spreading when testing actual malware
- May make it more extensible. Ie. easy way to clone the repo and get going without dealing with antivirus software, etc, etc.…
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I'm not able to compile the file "sim_waveform.vhdl" using Vivado (Version 2015.2).
I get the following errors:
```
ERROR: [VRFC 10-925] indexed name is not a time [/home/albert/git/dnk7/src/hw/PoC/s…
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Hello,
I wrote a JSON parser for the Hardware Description Language VHDL called [JSON-for-VHDL](https://github.com/Paebbels/JSON-for-VHDL?ts=2). My repository contains 5 projects for 5 different vendo…
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missing icon VHDL source code (text/x-vhdl)
does it should look like a text icon or not?
![Screenshot from 2020-10-08 19-59-13](https://user-images.githubusercontent.com/40562410/95472569-d8b3a000-0…
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MyHDL code below:
```
#!/usr/bin/env python
from myhdl import *
MAX = 16
def myhdl_b1(i, o):
c = intbv(4,min=0,max=MAX)
@always_comb
def rtl():
o.next = i + c
return rtl
i, o = [Sig…
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The purpose of this issue is to track bugs reported to maintainers of GHDL regarding compliance with these test suites.
- `vhdl_2008/tb_condition_operator.vhd`
- ghdl/ghdl#977
- `vhdl_2008/tb_m…
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Hi Nic30:
Is it possible to instantiate a VHDL or Verilog IP as a black-box component like [Spinalhdl](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Structuring/blackbox.html)? Thanks.…
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The ``.
Is there any way to replace the ligature for VHDL specifically (by IDE or otherwise) or do I need a separate font altogether?
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Attempting to compile using VHDL-2019 results in the following error:
Invalid VHDL standard 2019.
![image](https://user-images.githubusercontent.com/92508959/137267957-b8e9cadf-ce96-4976-a001-3e9ab5…
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I encountered a situation where Vivado could not process my HDL because a type "A" collided with a signal name "a".
GHC version: 9.0.2
Clash version: 1.6.3
Consider the following reproducer cons…