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In the [Setup](https://github.com/JulianKemmerer/PipelineC/wiki/Running-the-Tool#setup) instructions, the open source synthesis integration instructions call for the user to manually specify the paths…
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One of the new features of GHDL (which I am most excited about) is the "implicit standard version downgrade" that is achieved with `ghdl --synth`. I.e., we can take any modern and complex VHDL codebas…
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The FPGA implementation part of the Windows workflow keeps failing (cut-out from https://github.com/stnolting/neorv32/runs/3562298603?check_suite_focus=true#step:5:27).
```
yosys -m ghdl.so \
-…
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I am completely new to this project, but have installed and made all the required tools and they appear to work ok.
I created a simple half_adder.vhd file
library ieee;
use ieee.std_logic_1164.al…
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**Description**
If I declare constant under vunit bloc psl :
```vhdl
vunit i_mymodule(mymodule(mymodule_1))
{
//...
constant avalue: natural := 2;
//...
```
I get a GHDL bug in yosy…
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**Description**
I get a GHDL bug when I'm trying to use generate for detecting pulse in std_logic_vector :
```VHDL
-- generate pulse one cycle assertion
for J in 0 to 15 generate
…
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The [Microwatt](https://github.com/antonblanchard/microwatt/) CI has started failing with an error about a `$mem_v2` cell:
```
12.24.5. Executing OPT_CLEAN pass (remove unused cells and wires).
F…
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In the osflow setup, the guide is out of date. The first step is to run `make`, but this generates an error because the makefiles do not set `TOP`, `BOARD_SRC` and `DESIGN_SRC`.
I am referring to t…
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When using ghdl+yosys synthesis to simulate Microwatt in verilator, the register file is not available in a vcd trace. A simplified example:
```library ieee;
use ieee.std_logic_1164.all;
use ieee…
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When trying to compile the current git version (98f4594b67ef650b115653185022e46876fb08ce), the compilation fails with
`make
yosys-config --exec --cxx -c --cxxflags -o ghdl.o src/ghdl.cc -fPIC -DYO…