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While investigating https://github.com/antmicro/litex-rowhammer-tester/issues/7 I noticed that even in simulation there are problems with data read from memory over EtherBone.
The issue is that whe…
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When [enabling LTO](https://github.com/DurandA/litex/commit/15a6fc038727b3782870bdba04f5cae712afe79c) to compile the [LiteX](https://github.com/enjoy-digital/litex) bios, it GCC triggers an undifned r…
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I'm on macOS 10.14, and using Python 3.8.2 in an Anaconda virtual environment named `FPGA`. I installed `litex` by:
```
$ cd ~/Developer
$ git clone https://github.com/enjoy-digital/litex.git
$ …
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I got the following error when compiling the [LiteX bios](https://github.com/enjoy-digital/litex/tree/master/litex/soc/software/bios) when enabling LTO:
```
CC bios.elf
during RTL pass: expa…
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LiteX has evolved a lot and the current `SoCCore`, `SoCSDRAM` inheritated from MiSoC have evolved quite a bit in the last years and could be greatly improved now that we have a better idea of the SoCs…
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I am a bloody beginner, so this is probably very simple...
I was able to build and load. Flash gets stuck at 10% saying that a two read was not as expected. But from my understanding it should suffic…
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SDCard is currently working in SPI-Mode, SD-Mode should also be working (boot from SD-Card is already working) but still need to be tested/validated.
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Hi,
I am following this link: http://www.contrib.andrew.cmu.edu/~somlo/BTCP/
to create a RISC-V SoC that will be able to run Linux on it. I am using as a template the Nexys4DDR.
I can see that …
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I am trying to build versa_ecp5.py target from litex-boards with Ethernet support, using trellis toolchain.
`litex/litex-boards/litex_boards/targets$ ./versa_ecp5.py --build --with-ethernet --integra…
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**Is your enhancement proposal related to a problem? Please describe.**
ETH_NET_DEVICE_INIT takes a device-init function, and an API with an iface_api init.
The device-init, which is called first, s…