-
I have a large vhdl design that uses a few different vhdl packages in multiple locations. I'm having trouble stitching everything together in both the .sby file and my System Verilog testbench. I can'…
-
I am trying to move ara on VCS, but met too many errors, and they are hard to fix.
Do you have the correct Compilation Options on VCS or irun? Or a script of running by VCS?
These are examples of…
-
This ticket is a follow up issue to https://github.com/pulp-platform/pulpissimo/issues/104. I still have the same issue on a fresh master version of pulpissimo with a recent sdk (followed documentatio…
-
Hi all,
my understanding is, that the VUnit framework (always?) uses the "2-step flow" (-> vcom & vsim) of Questa, where the 'vopt' step is automatically applied during 'vsim'.
Unfortunaly, I need…
-
Coming from rodrigomelo9/FOSS-for-digital-HW-design#1
> Regards https://github.com/eine/vhdl-cfg, I thought about something similar between PyFPGA and others, such as edalize, hdlmake, tsfpga, and …
-
Hello all,
I am running a "NOT Gate"(language is verilog) as an example and i defined the tool is QuestaSim. but i am facing the serval issues:-
Traceback (most recent call last):
File "/home/u…
-
1. How to run regression inside the axi4Lite_avip project
2. How to check the coverage report and Assertions report.
Running the test cases using different tools like a Questa sim and Synopsys to…
-
Hi,
I've the following problem when I set the com_options:
hr.set_code_coverage("bcesf", "code_coverage.ucdb")
...
hr.add_files("../../../../01_RTL/bloc1/src/*.vhd", "my_lib", com_options='nofsm…
-
### Type
* Compile error (hopefully nobody has committed anything that doesn't compile!)
* Confusing or extraneous status or error messages
* Other.
### Steps to Reproduce
Try to build `spike_l…
-
### Description
https://opentitan.org/book/hw/top_earlgrey/index.html says to execute this command, and it executes successfully.
NOTE: the HTML does not say which directory to run in, it would be u…