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Hi,
Could you please let me know what maximum supported frequency of riscv in Xilinx device(like artix or virtex ultrascale, ultrascale plus)?
Thank you so much,
Duc
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RSD looks like it would be a super interesting addition CPU core option for the [LiteX Ecosystem](https://github.com/timvideos/litex-buildenv/wiki). LiteX already supports multiple different RISC-V co…
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## Bug
> cmd1.sc:2: object ops is not a member of package ammonite
> val res1_1 = interp.load.module(ammonite.ops.Path(java.nio.file.FileSystems.getDefault().getPath(path)))
> …
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Hi
As 1 miss => 1 refill (for the current config), i am wondering how to measure L2 cache **Write Back(WB)** of **specific cpu core**?
i am wondering how to update here ?
```
https://…
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We've been evaluating using VexRiscv for a project, and it's mostly been going beautifully. Even though nobody on our team knows Scala super well, VexRiscv and SpinalHDL so far is a hit because of how…
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after SpinalSim + Verilator windows setup according to https://spinalhdl.github.io/SpinalDoc/spinal/sim/introduction/
sbt "test:runMain vexriscv.MuraxSim" (using the latest github clone)
I go…
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This repository was created by merging the following resources:
- [ghdl/ghdl-systemc-fosdem16](https://github.com/ghdl/ghdl-systemc-fosdem16) (ghdl/ghdl-systemc-fosdem16#1).
- The content from sec…
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Hi, I am trying to run Linux in simulation. I followed the instructions in the linux.gen file but I get the following output.
INUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX…
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@Dolu1990 , The current MEM blackbox looks like several fixed interface forms(`Ram_1w_1ra` ,`Ram_1w_1rs`,`Ram_1wrs`,`Ram_2wrs`). It may not be suitable for ASIC design
Because of different teams or c…
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I'm not fluent with docker stuff, but https://github.com/SpinalHDL/SpinalDoc-RTD/actions/runs/11513946414/job/32051584090 failed because it seems the docker now use a too recent version of python ?
…