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How would I modify this to work on the VC707? Is it possible?
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**Describe the bug**
Can't compile with 2018.3 on Ubuntu 16.04
**To Reproduce**
Steps to reproduce the behavior:
1. /hdl
2. make all
3. wait
4. See error
**Expected behavior**
The success…
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This is not an issue, it is request for comments.
Do you mind anybody trying the branch in my repo for no pcie on vc707?
I am planning to make a pull request when I have time to bump them up to la…
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Hi Everybody,
this is a follow up question on the thread I did some time ago about importing the IPbus to the VC707 board. After the discussion we had at that time, I modified the KCU105 baseX exam…
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Hi I am trying to add some SPEC 2006 benchmarks onto the filesystem for Ariane to run them while being deployed through an FPGA (the VC707). Whenever I add the directory containing the benchmarks into…
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While trying to make this for the VC707, I hit this error, where there is no add_sources.tcl file.
read_ip xilinx/xlnx_axi_quad_spi/ip/xlnx_axi_quad_spi.xci
read_ip xilinx/xlnx_clk_gen/ip/x…
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I tried using connectal with [open-source version of Bluespec](https://github.com/B-Lang-org/bsc/) and it fails.
There seems to be some outdated switches in connectal and include locations in regards…
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I try to debug freedom with openocd on the board vcu118 but could not find configuration file for the board. Has anyone tried that? I have no idea where to get this file ... Thanks a lot.
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In order to fit [sifve-inclusivecache](https://github.com/sifive/block-inclusivecache-sifive), I bumped rocket-chip newer to [bcb3d0a](https://github.com/chipsalliance/rocket-chip/tree/bcb3d0a9c097a4d…
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Hi again!
I wonder if it is possible to run simple bare metal test on the system you provide. I think so (it is able to boot Linux!), hence I'm trying to find a way.
I find myself a bit confused, …