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**Describe the bug**
When trying to generate Verilog for a fairly complex module written in DSLX the compiler segfaults.
**To Reproduce**
Steps to reproduce the behavior:
- Follow the XL…
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Hey repo contributors,
I found that std_slice is combinational but std_bit_slice is not. However, from the verilog template, they should be the same.
I wonder why you have such design.
```ver…
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I'm looking to use Cascade for Sodor cores (1-stage, 3-stage, 5-stage) and I've noticed Cascade relies on an SoC model of the core and uses Verilator to compile the model to what is actually being fuz…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything rel…
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The target UART speed is configured inside the SOC module as 1.000.000 baud. However the real output rate on the UART USB adapter is well below the target value. This is the baud rate setting in SOC.v…
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Error detected while processing /home/bhargavrajp/.vimrc[3]../home/utils/vim-9.0.0630/share/vim/vim90/syntax/syntax.vim[43]..BufRead Autocommands for "*.sv"..FileType Autocommands for "*"..Syntax Auto…
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Ngspice team has recently added two XSPICE devices: `d_process` and `d_cosim`. These devices allows to simulate the component defined as Verilog/VHDL code with analog schematic. It's need to add suppo…
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[nn_verilog_a_l0_2_l1_2_l2_2.va.txt](https://github.com/pascalkuthe/OpenVAF/files/14942978/nn_verilog_a_l0_2_l1_2_l2_2.va.txt)
[openvaf-crash-1712820826.log](https://github.com/pascalkuthe/OpenVAF/…
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The vpr contains server mode functionality, where the vpr acts as a server instance, waiting the client's requests.
In order to check that feature in work we actually requires the separate client a…
w0lek updated
2 weeks ago
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#### Expected Behaviour
We should have no compiler warnings.
#### Current Behaviour
Some warnings in vqm2blif:
[ 50%] [BISON][VqmParser] Building parser with bison 3.8.2
/home/runner/work/vtr…