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I am working with Dirk Koch's group on eFPGA fabrics, and one of the key use cases we have in mind is dynamically adding instructions to CPUs, and I think it would be useful to make sure that's consid…
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1. I find that you use ```riscv32-unknown-elf-objcopy``` and ```hexdump``` to convert the ELF file to HEX file for simulation/FPGA BRAM initialization . I think you could have a look at https://githu…
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in the generated synthesis .v file, i found some of the flipflops connected to ouptut pins,(flipflop to output)
but while pathgroup flops to output ,sta tells no paths found
why? and how can i fix …
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### Description
I am running the design flow example using picorv32a design. I am using commit e910d115dc75c51407f652330bce8ed997c45946 and I have all steps successful up to run_routing, where I am g…
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In the following section, in `picorv32.v`:
```
for (i = 0; i < 32; i = i + 1) begin
assign gpio_all_dat_o[i] = |(gpio_dat_o[i][`OPENFRAME_IO_PADS-1:0]);
end
```
``[`OPENFRAME_IO_PADS-1:…
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INTENTION: to set path groups, so we need list of inputs ,registers and outputs from sta tool after reading sythesised verilog.
now,after reading liberty,verilog and linking the design ,all_inputs,…
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I have followed the instructions in cores/picorv32 and installed the oss-cad-suite from the latest tar-file. Running `make -C checks -j1` generates the following error message:
```
make: Entering di…
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I'm interested in getting litex to work fully with the tang primer 20k, so I can try some riscv rust programming on it. Without the dram things are kinda limited (the dram is way overkill, but I want…
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Minimal parsing of commands and responses (limited to just their sizes) must be done on FPGA side in order to properly set status bits that host can use to check whether TPM expects more bytes of comm…
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I was trying to run `make test` with my existing 32-bit compiler, I got the following error:
```
[...]
python3 firmware/makehex.py firmware/firmware.bin 32768 > firmware/firmware.hex
vvp -N testbe…