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Hi,
This is actually a question. I have synthesized Neorv32 in Design Compiler. My problem is with the resulting design file that I produce with design compiler. It actually gives 'X' signal in simul…
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The cancelation of an coroutine task results in the errorlog below.
I am using
```
cocotb 1.8.1
cocotb-bus 0.2.1
pyuvm 2.9.1
```
A minimal example to trigger this mig…
Febbe updated
6 months ago
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A simple try-out of vfmv.f.s and vmv.x.s causes the simulation to error out.
Does ara support vfmv.f.s and vmv.x.s?
Thanks.
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I think it would be a nice feature to allow the user to use a flag to display all signals at a user-specified hierarchy depth when they pass the `-g` flag to open the GUI. I get really annoyed having …
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@cocotb_test
async def my_test(dut)
driver=BitDriver(dut.clk, dut.data_in)
cocotb.fork(Clock(dut.clk, CLK_PERIOD, units='ns').start())
driver.value = 1 driver.start()
await ClockCycles(dut…
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Hi
**My question**
I imported NeoRV32 micro controller into a questa simulation project and used `sim/simple/neorv32_tb.simple.vhd` and `sim/simple/uart_rx.simple.vhd` for simulation. I wondered w…
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We are simulating Sargantana with both Verilator and Questasim with the necessary options to generate the files in kanata format to visualize the pipeline. The files seem to be generated correctly but…
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Hello, i want to simulate llama llm (the version on c++ that there is an option to cross compile it and simulate the riscv edition with vector extension) on ara. I successfully installed all the tool…
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Hello, when I run VUnit test the ModelSim spits out a warning regarding the `string_ops`
The warning is: `\vunit\vhdl\string_ops\src\string_ops.vhd(565): (vopt-1083) Implicit array operator "=" alwa…
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Hi! While playing around with `do_fuzzdesign.py` for the cva6-c1 CPU, I have noticed three program descriptors whose "bug" correspongs to `list index out of range`. The descriptors in question are as …