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This repository was created by merging the following resources:
- [ghdl/ghdl-systemc-fosdem16](https://github.com/ghdl/ghdl-systemc-fosdem16) (ghdl/ghdl-systemc-fosdem16#1).
- The content from sec…
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when I using spinalhdl to generate a verilog file specifically for mem simulation, if the array used for initialization is too large (probably width * depth exceeding 240MB), it will cause the follow…
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RSD looks like it would be a super interesting addition CPU core option for the [LiteX Ecosystem](https://github.com/timvideos/litex-buildenv/wiki). LiteX already supports multiple different RISC-V co…
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My Linux verilog generating environment is sbt 1.10.0 (Red Hat, Inc. Java 11.0.23). when using sbt "Test/runMain vexiiriscv.Generate" to generate verilog, the terminal reports the error information as…
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The current usage is as follows:
```scala
NaxScope.create(xlen = 32)
val frame = new MyPlugins(plugins).framework
```
Can the parameter configuration and auto-negotiation mechanism be general…
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Hello,
I am currently trying to generate linux image to simulate linux booting on VexRiscv.
To do so, I follows guidelines in src/main/scala/vexriscv/demo/Linux.scala:
```
Buildroot =>
git cl…
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AMBA5 CHI could be a good choice for high performance cache-coherent NOC design. However, it is kind of complex. How about building a NOC library with AMBA5 CHI? We can find its' specification book an…
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Hello,
A feature idea for a far future:
Designers can use [Wavedrom](https://github.com/wavedrom/wavedrom) to [easily build waveforms](https://wavedrom.com/editor.html) with inputs and outputs o…
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I try to generate verilog by using the intelliJ IDEA, sbt 1.10.0 (Oracle Corporation Java 1.8.0_301) but now it reports
C:\Users\pzhao\Downloads\VexiiRiscv-dev\ext\SpinalHDL\core\src\main\scala\spina…
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It would be nice if VexRiscv had support for vectored interrupts. Basically something like fast interrupts in [Ibex](https://ibex-core.readthedocs.io/en/latest/exception_interrupts.html).