-
```
localparam string TESTED_VERSIONS[] =
{
"2023.1",
"2023.2"
};
```
$ svinst test.sv
files:
parse failed: "test.sv"
test.sv:72:42
|
72 | localparam string TESTED…
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This issue contains stages of adding ARC changes to upstream openocd project.
First supported board is going to be ARC EM Starter Kit, then HSDK.
I outlined the first major stage, which will contain…
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eTeak as the same as its predecessor counterpart, the Balsa synthesis system, reports area estimation of the generated Verilog circuit. However, this highly depends on the utilised cell library (ASI…
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When I try to use custom commands, I always get an error 'p not supplied'. There are no further logs to diagnose the problem
```
- task: synopsys-coverity@1
inputs:
coverityService: 'coverit…
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Hi, thanks for this great tool but have run into some issues.
Trying to build and install ghdl locally to use ghdl-ls with emacs on a fedora 36 machine. Don't have admin access on the machine so a…
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### Describe the bug
Hello
I found that the SMBus block reading feature of the Synopsys DesignWare I2C adapter of raspberry pi 5 doesn't work.
As shown in below snapshots in green box.
A sla…
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As of today FTrace is not supported for ARC processors, while it is a very powerful tool for kernel tracing, see https://docs.kernel.org/trace/ftrace.html#wakeup as a good example.
What's good thou…
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Could you add the iotdk flash driver support into openocd?
So users can download their program into iotdk's flash through gdb and openocd
Iotdk has two flashs supporting XIP
* internal efl…
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Hi Stephan. I've been trying out the Audio Class implementation for a while now, and have run into a problem I cant seem to figure out. My devboard only seems to receive every second frame from the ho…
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The parser is failing when a logic is called 'inf':
test2.sv:5:13: syntax error, rejected "inf" (syntax-error).
Short summary.
verible-verilog-lint test2.sv
```systemverilog
module fred…