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**Describe the bug**
Not sure if this is a bug, and what to do about it.
**To Reproduce**
```
module t;
function automatic [31:0] test();
for (int i = 0; i < 3; i++) begin
test = …
udif updated
7 months ago
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Thanks for taking the time to report this.
**What would you like added/supported?**
Enhance Verilator to include compile and runtime statistics in its output:
- Compilation Time: Report the C…
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I just imported a quartus project into TerosHDL, and I can't manage to compile it with TerosHDL, although it works from Quartus.
I get the following error:
```
Info: Elaborating from top-level …
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I would like to use `Enum` to implement the design.
Currently, I can write the statement like
```
if (s.opcode == Opcode.LUI_OPCODE.value) | (s.opcode == Opcode.AUIPC_OPCODE.value):
s.opco…
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#574 の日本語版
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# VerylによるRTL設計の漸進的な進化
VerylはSystemVerilogの代替言語として設計されたハードウェア記述言語です。特に既存のVerilog/SystemVerilogコードベースを漸進的に改善することに着目しています。
「漸進的」とは既存のコードベースの一部を徐々にVerylに置き換えていくことが可能であることを意味します…
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Use the wiki to see the list of tools:
https://fpga-mafia.github.io/fpga_mafia_wiki/docs/TFM/welcome
### Very important:
Make sure to document anything that did not work so we can add it to the d…
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Please add SystemC temporal assertions implementation described [here](https://github.com/intel/systemc-compiler/wiki/Immediate-and-temporal-assertions-in-SystemC).
These assertions are intendend t…
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Hi, trying to track down an issue, I believe it's in the plugin but it could also be in surelog.
I am using the default submodules except for https://github.com/chipsalliance/yosys-f4pga-plugins/pu…
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I am attaching the list of sample errors list here
Generated CODE:
`
always_comb begin
automatic logic [4:0] next_c = field_storage.CSR_MAC_ADID[i0].csr_mac_adid.value;
automatic logic load…
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The following code does not compile in iverilog. I believe this is valid systemVerilog code. At least one commercial tool accepts this happily. iverilog seems to be unhappy about the datatype and w…