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The entire project run without any simulation errors. The input and output locations are also given properly.
But was unable to get the outcom.bmp file as output image.
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Hi,
I followed the last developments of the openwifi project with high interest and I have successfully started the release Notter 1.4.0 by using the "zed_fmcs2-board".
In the following I would…
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@nickg this is an issue that I have found while working on a project, which I haven't been able to solve.
A `fatal: load indirect with non-pointer argument` error is produced when trying to elabora…
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Dear developers,
Vivado has an excellent interface to questa so that one can switch a RTL simulation from xsim to questa with few clicks. Vivado automatically generates compile, elaborate, and simu…
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Hi,
I am currently testing this compiler and I had a problem simulating the generated SV modules with different tools.
I have implemented a producer and a consumer module that communicate via a …
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Hi,
I'm a hardware designer looking for some available fft core in verilog or vhdl and find out your great contribution here. But this repo does not seem to be complete. **There is no testbench fo…
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**Description**
**GHDL** fails to analyze the **ModelSim** `mti_util.vhd` library file.
**Expected behaviour**
I would expect **GHDL** to analyze the **ModelSim** library source without any i…
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Hello there,
I want to use my FPGA-based EDA tool (similar with Zebu from @Synopsys) to run a single-core SoC. It utilizes Xilinx Virtex Ultrascale _XCVU440_ FPGA boards.
My current step is to …
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This was tested on latest Git master.
I tried the following shorter examples **not** causing a crash:
- generate case string + processes to print MODE,
- generate case string + entity instance wi…
jeras updated
9 months ago
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Greetings,
I'm currently trying to get into SpinalHDL,
and to use XSim simulation on Windows.
In the test project's `Config.scala` I changed the `def sim = SimConfig.withConfig(spinal).withFst…
oletf updated
9 months ago