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Can we have support for synthesising necessary files for the 100t variant of digilent arty kit?
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## Description
We would like to introduce a scala API that actively validates the feasibility of tensor operations while being written, NOT while being tested or deployed. The API will be based on …
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Hi
my openocd missing jtag_tcp.cfg, where is this file?
thanks
Peter
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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Kind of a sub-thread of #137 specific to resets.
At the moment, all statements are generated implicitly inside a block that only runs when the system is running. This kind of makes sense when writi…
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1.Hello, prior to this, I successfully ran a nax_soc using lite according to your tutorial, but its nax_core core interface is AXI4_lite. I want to use AXI, but I entered axi in the -- bus stand param…
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### Feature Description
Hi,
The fact that your flow supports different design languages is really great.
I wonder if there is any plan to support other languages such as spinalHDL, rohd, veryl?
…
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Someone has used these two libraries-Apb3SpiXdrMasterCtrl.scala and SpiXdrMasterCtrl.scala, Can you explain this usage, including the configuration of various parameters, whether it is suitable for du…
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**Note: this issue is on the public repo**
## Interpretation of Venkat point
As I understand what Venkat mentioned during the review, is that the current documentation enumerates the hardware, RTL a…
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use the Vexriscv,and generate the MuraxSOC(InitRam).running on FPGA board, the UART and GPIO(Blink led) are working.
when I use the openocd connect the core,
"Error: dtmcontrol is 0. Check JTAG con…