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There are quite a few Ethernet MAC cores, but mostly in Verilog. I've a project written in VHDL, use GHDL, and therefore looked for a core written in VHDL, and found this project.
The core was tested…
wfjm updated
3 months ago
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Hi,
I have hit the following issue with Signals with a set value (like `lsr = Signal(intbv(0x2eb1edd0, _nrbits=30))`. If, on conversion to VHDL, I use the parameter `initial_values=True` it generat…
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Hello,
my cocotb-version:1.8.1.
Deposit works as a force command on GHDL. In addition, it is impossible to release it.
For example with this vhdl code and cocotb test:
```
process (clk, resetn)
…
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## Describing the bug
By pressing the 'Schematic Viewer' button on the 'Dependency Tree' panel, the Schematic Viewer window shows a blank page.
In the same time, the Output page for 'TerosHDL: Glo…
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When will support for VHDL be added (`.vhd` and `.vhdl`)? I would guess this is similar to Ada, so probably not much work there. SystemVerilog (`.sv`)should be the same as verilog.
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Hello,
I have a very basic test bench with a vhdl top and two sub-modules: one vhdl and one verilog.
When trying to access the verilog submodule from a cocotb TB I have an error:
Unable to cr…
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Add support for bringing VHDL types into Python.
The obvious ones are enumeration and physical types.
**Enumeration type**
```vhdl
type MULTI_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING, AMBIGU…
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VHDL process details which were specified inside a process aren't in output.
Particularly global scope tags like \todo and self-written aliases get lost.
The attached example was generated with …
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I am just beginning to review the VHDL version,
please could this expression be elaborated?
ie is this a defect of the implementation?
or what is the reason for its inclusion?
It has been applied …
peepo updated
2 years ago
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We are not sure if we have the right VHDL source code version for the firmware we are using to run the Test Bench.
- We have one version of VHDL source code but
- we are not sure how to compil…