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I would like to ask what is the state of support for SV union with the git versions of the plugin and yosys.
For now I can see there is no outright error stating unions are not supported as was there…
jeras updated
2 years ago
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- [hdl/constraints: board](https://github.com/hdl/constraints/tree/main/board)
- hdl/constraints#2
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1. Memory.hdl
2. Computer.hdl
https://www.nand2tetris.org/project05
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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Hi,
I analyzed the VHDL code from your surf project with Linty: https://oss.linty-services.com/dashboard?id=surf&codeScope=overall
Do not get scared by the number of issues :-)
It's just to pro…
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I tried hdlparse for parsing a small entity. The entity is known to be correct (used in many projects and working fine for synthesis and simulation). However, hdlparse just returns and empty list. Let…
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Hi ,
I see that library is buffering the data internally is there a way to stop buffering so that when I can call send the data is delivered to network socket as soon as possible in and tcp sockets h…
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Is it possible to use two instances of hdl controller in one node red projecf?
When I try to use 2 hdl controller gateways,one of the gateway stops giving status.
In my node red project I have :
h…
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In file included from /usr/include/pcl-1.10/pcl/pcl_macros.h:77,
from /usr/include/pcl-1.10/pcl/PCLHeader.h:10,
from /usr/include/pcl-1.10/pcl/point_cloud.h:47,
…
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Hello,
I am trying to simulate a larger top level design (entire Series-7 FPGA), featuring several transceiver-based IPs. So far, I have been able to simulate this design when not using VUnit (just…
anro7 updated
3 years ago