-
I think it might make sense to group the generators into some categories;
* Analog generators (BAG / OpenFASoC)
* FPGA/CRGA generators (OpenFPGA / Fabulous)
* CPU generators (rocket, vexriscv,…
-
Hi, I was simulating my design and I realized there might be a mismatch between verilog simulation code and the description in OpenRAM paper.
![image](https://user-images.githubusercontent.com/5198…
-
Project extended to 14 week. New deadline for midterm completion and evaluation- Aug 3.
Complete RTL-GDSII section "Running the Automatic RTL-GDSII flow" using design with key Flow stages using mem_1…
-
![image](https://user-images.githubusercontent.com/56708718/143862404-f05271a3-eccb-45c5-a352-8c3b0628829e.png)
I cannot seem to figure out the issue with the control size. I am currently trying to…
-
So I am trying to use this library alongside the [ESP32-HUB75-MatrixPanel-I2S-DMA](https://github.com/mrfaptastic/ESP32-HUB75-MatrixPanel-I2S-DMA) to display scrolling images with an LED matrix. I sta…
-
Continue after fixing setup described in https://github.com/VLSIDA/OpenRAM/issues/137
Thanks again!
```
SP: ...OpenRAM/temp/sram_32_1024_sky130.sp
ERROR: file stimuli.py: line 50: Must define ei…
-
Hi, I generated SRAM macros with OpenRAM, since I needed nearly 40 kB of RAM and it is almost impossible to provide it with 2 kB macros. I got Magic DRC errors and asked about it in the sky130 Slack c…
-
I'm a researcher on in-memory computing. Is this tool capable of generating SRAM arrays with customized cells (like the 8T or 10T cells)? It might be helpful for my project. Can I manage that by follo…
-
### Description
Hi, when I run any design, in IO placement stage I encounter this error.
```
Error: ioplacer.tcl, 54 can't read "::env(FP_IO_HLAYER)": no such variable
[ERROR]: during executing op…
-
Hi,
These files (especially the tech.py) were taken from OpenRAM, which is ok, but you need to include our copyright which is the restriction of the BSD license. Thanks!
Matt