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my solution:
```scala
val allReady = io.outputs.map(s => s.ready).asBits()
val low = util.lowbit(allReady)
val unbusy = allReady.orR
val num = OHToUInt(low)
```
it's a one cycle dispatc…
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I'm working on the Counter lab and got it to compile successfully (thought I don't know if my solution is actually correct): `sbt "runMain workshop.counter.CounterMain"` outputs the following (where t…
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So I flashed a blinky onto my pico-ice board using SpinalHDL and apio. Hurrah. Now I am trying to synthesize the J1SC for the Pico-Ice board. Oh boy, it is quite tricky. There is a lot of stuff in…
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Pre-scriptum: sorry for the long text
It is possible to [add Rust code into documentation](https://doc.rust-lang.org/rustdoc/write-documentation/documentation-tests.html) (equivalent of scaladoc). …
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Hi,
I am having an issue with Vivado implementing a large number of BRAMs in the DCache. It appears that each byte in the cache is being implemented as an RTL RAM and then replaced with a BRAM for …
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Because of #607, I thought about exchanging Verilator for IVerilog and see if it helps. Adding `simConfig.withIVerilog` and then running it again gave me the following:
```scala
[Progress] IVerilo…
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Hi,
Here is were i'm reporting the FMax mesurments and progress.
For VexiiRiscv (set as toplevel, after some tunning) with :
- RV32IMACSU + 4\*4KB I$ + 4\*4KB D$ + D$ hardware prefetcher + st…
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I'm trying to write a simulation bench for an AXI slave DUT. It seems like one should extend these abstract classes and override `genAddress`, `mappingAllocate` and `mappingFree` and then call `genCm…
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I wondering if something like this can be adjusted. Similar to https://github.com/SpinalHDL/SpinalHDL/issues/132. If I have a Bundle that I use up a hierarchy, outputs seem to get reassigned.
Here …
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I wanted to ask if VexRiscv would support the RISC-V vector extensions sometime in the future. Thanks!