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按了几个插件之后就突然不行了，现在将之前的无关插件都卸载了，也不行
qgzln updated
2 years ago
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When I activate the plug-in, the "begin end" code block changes from multiple colors to only one color
![图片](https://user-images.githubusercontent.com/49726805/146116615-f3032b5a-362d-4733-84d0-e5aee…
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Today I updated to 5b9806ae6d8a0311f941ac453267b3c79033c864 and noticed some regressions.
I recompile Verilator rather often and this issues are probably from one of Feb 27 commits.
I have not bisec…
jeras updated
2 years ago
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I'm working through the Symbiflow examples and modifying some using VS Code with the "Verilog-HDL/SystemVerilog/Bluespec SystemVerilog" plugin. So far I've seen, it does a good job at highlighting syn…
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你好，我用verilog实现了一个FTDI245H FIFO接口的控制器，看您这里的systemverilog好像很简洁，请问该如何去学习systemverilog呢？
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不知道为什么input和output不能正常高亮
我之前一直用的Verilog-HDL/SystemVerilog/Bluespec SystemVerilog插件，但…
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Hi,
I'm trying to implement DPU-TRD with custom board follow DPU-TRD Vitis flow. The tool version is v2020.2 and Vitis-AI v1.3.2. I follow these two tutorial :
https://github.com/Xilinx/Vitis-Tu…
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SiliconCompiler is an open-source Python-based build system for ASIC design tools.
## Several pipecleaner designs
For this project, we would like to build a variety of small but realistic digita…
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First of all great work with this tool, we have been using it extensively in our build process.
There is a functionality recommendation that will add more impact to this work.
At the moment, Xil…
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`hdl_checker` appears as not running (`:LspStatus`)
```
if executable('hdl_checker')
au User lsp_setup call lsp#register_server({
\ 'name': 'hdl_checker',
\ 'cmd': {server_inf…