-
Hi all,
I have a problem with the axi_xbar: I use a configuration with 4 masters and 2 slaves. The second master writes valid data to the interconnect and the data is confirmed by the slave, but by…
-
By sticky, I mean the behaviour described in the standard (I only have 2001, section 27.32 describes the function):
`When vpi_put_value() is called for an object of type vpiNet or vpiNetBit, and wi…
-
I have seen that a post about ChiselSim has been recently published. It says that ChiselTest is not longer supported for new chisel features.
So, what are the future developments for chiseltest?
-
Hi,
With regard to:
https://github.com/svunit/svunit/blob/5b785137a7563ac0b145fa660c2529bb33037d9d/svunit_base/svunit_internal_defines.svh#L22-L27
I get the following output.
```
$ runSV…
-
error report:
```
Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06-SP1_Full64; Runtime version P-2019.06-SP1_Full64; Aug 28 10:4…
-
I'm a newbie to Verilog but I'm seeing a difference between simulations run with iverilog 12 and ISim (14.7) and I think it may be a bug in iverilog. I'm attempting to simulate a verilog module I'm d…
-
### Description
Between the 16. and the 19. of October something caused the entropy source coverage to plummet to around 30 to 40%.
To verify this I ran the following command with a 0.1 reseed-mul…
-
### Type
* Functionally incorrect behavior
### Steps to Reproduce
Branch: `cv32e40s/dev`.
Hash: Latest or `47a423f0`
```
cd cv32e40s/sim/uvmt/
make test TEST=fencei USE_ISS=0
```
The ISS …
-
Hi @Dolu1990
There is a simple example:
```
import spinal.core._
import spinal.lib._
import spinal.core.sim._
case class bootTest() extends Component {
val pc=out UInt(8 bits) setAsReg() ini…
-
Hello, I am investigating in using ibex for my University research project and I have some problems trying to get the example (targeting Artix A7-100T) to build correctly. I took a look in the example…