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when I run command: make buildfile CONFIG=TinyRocketConfig. Errors below came out and terminate in the end
[error] INFO: unable to compile data_arrays_0_0_ext using SRAM2RW64x4 port count must …
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Hi! I would love to use some of the code you have here. Could you please specify under which license is this repo?
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While reading https://spinalhdl.github.io/SpinalDoc/spinal/sim/introduction/, I wondered whether any effort has been done in order to replicate the workflow with VHDL sources. [ghdl/ghdl](https://gith…
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Refactor to support Verilog-AM/S simulations
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Error occurs when running testbenches under verilog/dv,
`caravel_user_project/caravel/verilog/rtl/caravel_netlists.v:89: Include file mgmt_core_wrapper.v not found`
/caravel does not include proper …
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Sorry for opening many tickets recently, I'm trying to move all our test cases to cocotb-test. I hope you don't mind.
For mixed language simulations, sometimes different compiler arguments are need…
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The following things need to be done to complete the Qt5 migration. The Qt5 port is located here: https://github.com/ra3xdh/qucs_s/tree/qt5
- [x] Import Qt3 compatibility classes from Qt4 source; …
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Hello, I found out in your docs that eventually you would like to add simulation support to slang.
I was wondering what would be the roadmap / directions there? Also, where would you suggest
start…
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I read issue https://github.com/ra3xdh/qucs_s/issues/37, which says that Verilog cannot be integrated into Ngspice and XYCE. Does this also mean they do not support VHDL?
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I'm seeing a relatively dramatic slowdown (25x--100x) compared to the old Chisel2 version of Rocket Chip. This is getting hit from both the Chisel3 version running a lot longer (10x the cycles) and th…