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Hi,
I am trying to use OpenCL SDK 17.1 (Quartus Standard ) with De1SoC
I am having a couple of problems
OS Ubuntu
Intel SDK installation
Quartus Prime Lite 17.1
Intel FPGA SDK for OpenCL 1…
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When I run Quick demo with opae driver, there are meaningless performance prints. it seems to take place only in opae driver.
`test-pc@testpc-desktop:~/vortex/build$ ./ci/blackbox.sh --driver=opae …
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Hi there,
I seem to be having some issues using the modelsim linter. It is installed, and I have put the installation directory (`C:\Program Files\IntelFPGA\modelsim_ase\win32aloem`) in my `PATH` v…
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HI, I'm a master student from Brazil, and I'm working on a project that uses the PULP platform.
I'm having difficulty when I simulate a test with ModelSim, a message appears saying that there was a…
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**Describe the bug**
I'm trying to compile a simple SDFG for an Intel FPGA, however I'm getting the following errors:
```
/usr/include/CL/opencl.hpp: At global scope:
/usr/include/CL/opencl.hpp:…
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Hi,
when configuring PoC for Intel Modelsim Starter Edition, I encountered the following problem:
```
Configuring installed tools
---------------------------
Configuring PoC
Installation dir…
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There are several warnings that I am not sure matter or not. And finally, there is an error thrown.
```
cd t2s/tests/performance/qrd
g++ qrd-mgs-batch.cpp -g -I ../util -I ../../../../Halide/inclu…
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On `master`, using GHC 9.6.2, I'm seeing:
```
$ cabal run clash-testsuite -- --no-vivado -p IntegralTB.SystemVerilog
Warning: Requested index-state 2023-06-17T22:28:17Z is newer than
'head.hacka…
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@cdsteinkuehler
@mhaberler
@ArcEye
@machinekoder
Just a small heads up on something on my TODO list comming true:
Finally :-)
IntelFPGA in their upcomming 19.1 Lite release (not yet dow…
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Hey guys!
I dont have a de10soc , but i have a de1soc(board).
I would like to know if anyone has tried to implement this fantastic work in it.
Do you think it is possible to implement on the de1soc…