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# Repository Creation Request
1. ## Coordinating Institute: _Indian Institute of Technology Kharagpur_
2. ## Virtual Lab Name: _Digital Electronic Circuits Virtual Laboratory_
3. ## _Phase II re-…
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Hi,
I'm trying to check the area breakdown of the plugins in Vexii (like the area of IntAlu, Lsu or Branch).
Is there a way to generate plugins as separate verilog modules? Or are there any other…
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### Feature Description
Hello,
I have some RTL code that passes through the flow in Yosys 0.44. It seems like the Yosys version has been updated to 0.46.
Now floorplanning fails with the following…
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I am trying to run peakRDL regblok on a block that we are designing. Currently, we are using ORDT,
but since the ORDT is not mainteined anymore, we might be looking for alternatives.
I see that th…
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I've been noticing this issue over the last few weeks (beyond just 5 questions being missing, entire sections are missing)
I am adjusting both AI Profile and Space Prompt with this adjusted text:
…
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Get following error when running the attached design (using logic cell macro):
Writing Implementation Netlist: top_post_synthesis.v
Writing Implementation Netlist: top_post_synthesis.blif
Writing…
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**Description**
When using the GHDL plugin to yosys, and probably more generally, attributes are not attached to instantiations. This causes (for example) yosys to optimise away instantiated blocks …
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Hosting/Rehosting
Request for " Digital Electronic Circuits Laboratory" IIT Kharagpur
Lab Name: Digital Electronic Circuits
Laboratory
Disci…
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This is not a bug, I would just like to discuss some of my findings.
I choose VexRiscv, since it seems to be the the most prominent FPGA implementation of RISC-V.
I did not synthesize VexRiscv mysel…
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Spun out from #9391. We want to check how synthesis tools treat casts from a logic vector to an enum variable of the same size, e.g.:
```systemverilog
parameter int MuBi4Width = 4;
typedef enum…