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#### Expected Behaviour
We should have no compiler warnings.
#### Current Behaviour
Some warnings in vqm2blif:
[ 50%] [BISON][VqmParser] Building parser with bison 3.8.2
/home/runner/work/vtr…
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As for know, Odin doesn't support SystemVerilog. I think of using Verific as frontend tool to parse systemVerilog and even verilog for Odin. I tried to do so and parse the designs using Verific then…
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Reproduction steps:
- Open a fully annotated schematic.
- Bring up the BOM generation dialog.
- If no plugins are present, just add one from the list of packaged plugins.
- Try to generate a rep…
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Fourier analysis with `.FOUR` gives no output if the latest Xyce v7.4 is used. The Qt4 Qucs-S version is affected too.
- [x] Change `.FOUR` output file name extension
- [ ] Add support for Parame…
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While dealing with https://github.com/SymbiFlow/python-fpga-interchange/pull/108 I have bumped into one issue which has many ways of being solved IMO.
The problem is that the XDC constraints that a…
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To enable LEC'ing FPGA designs, we need a means of translating, e.g., LUT4-based designs into AND/OR/NOT/etc.-defined netlists, since that's the language our LEC tools currently speak.
julianviera@…
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I am working/learning my way through SpiceSharp and have decided to convert the GUI app to UWP. Would you please provide me with a NetList sample which generates output ( one that works with your WPF …
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I have edited a netlist in SpiceSharpGUI and it runs successfully. Then I want to use SpiceSharpParser to parse the netlist. However, I get several errors when I copy my netlist to the SpiceSharpParse…
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I noticed that `qucsconv` ignores input lines starting with spaces for spice netlists:
I saw this trying to use the [spice model for the LM358 on the TI website](http://www.ti.com/lit/zip/sloj045) , w…