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**Type of issue**: other enhancement
**Impact**: no functional change
**Development Phase**: proposal
**Other information**
Since rocket chip has been refactored to chisel3, and we hav…
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Hi, I am trying to use already present hardware accelerator in Rocket chip. To use it I am doing the following step:
1. In freedom/rocket-chip/src/main/scala/coreplex/Config.scala adding this
class…
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Hello, I am attempting to configure a NOC within Firesim version 1.18.0 by utilizing rerocc, with a configuration featuring 5 Rocket cores and 10 Gemmini accelerators. Despite having successfully gene…
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Hi freedom team :)
I want to modify DefaultFreedomEConfig because i need fpu, the default config doesn't has fpu.
This is a default config:
`class DefaultFreedomEConfig extends Config (
new Wi…
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Hi Team,
we installed rocket tools and chisel in machine and set the path, when we run the cmd "make verilog" in rocket-chip we are geeting attached error. Can you help me on this issue please
…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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Hi everyone, I am a newbie in Chisel.
Does anyone has experience in that case, please help me?
Thank you so much for any kind helps.
My goal is to add a instruction detecting signal (in particula…
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The background is in the RocketChip, we need metadatas for instruction decoding, rather than instruction name and bitpat only. For downstreams like us, which need to parse instruction metadata from ri…
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At global scope:
cc1plus: warning: unrecognized command line option ‘-Wno-parentheses-equality’
VTestHarness.mk:69: recipe for target 'SimDTM.o' failed
make[1]: *** [SimDTM.o] Error 1
make[1]: Lea…
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**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**Other information**
https://github.com/riscv-boom/riscv-boom/issues/659 seems related.c
https:…