-
* https://github.com/riscv-collab/riscv-gnu-toolchain#installation-newliblinux-multilib
> The musl compiler (riscv64-unknown-linux-musl-) will only be able to target 64-bit systems due to limitatio…
-
The xtheadfmemidx doc says "All instructions are available for RV32 and RV64". But th.flurw seems identical to th.flrw on RV32.
I found this patch that removed some of the "u" instructions from RV3…
-
### The issue
- Running riscv32 userland with riscv64 kernel is broken
### Steps to reproduce
- Use those firmware/kernel/rootfs: [rv32_umode.zip](https://github.com/LekKit/RVVM/files/14801669/rv…
-
Some instructions have different encodings between RV32 and RV64.
From the RISC-V ISA Specification (20191213), Chapter 24, "RV32I Base Instruction Set":
![image](https://github.com/ThinkOpenly/sa…
-
### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
According to RISC-V ISA specification, for RV32, the bit 25 of instructions `BCLRI`, `B…
-
Due to 2x`XLEN` stack alignment, RV32 eabi needs extra compressed instructions to efficiently operate on 8 byte aligned stack, otherwise non compressed instructions will have to be used when limiting …
-
hello,
I tried to simulate a few toy programs with `forvis` aka RISCV-ISA-Spec-exe. But up to now, it did not succeed. Are there any specific configuration settings, or compilation settings to kn…
ghost updated
6 years ago
-
HLIF is a 64-bit communication channel that exists at `tohost` and `fromhost`. This channel is used for early boot, syscalls, and for shutting down the simulator.
Operations are performed by writin…
-
Hello,
We have tried to implement RV32M extension instruction, please have a look. The extension instruction also passes riscv-test benchmark. If you want your riscv-atom to support RV32M, you can l…
-
On RV32 if `minstret` the lower 32 bits of `instret` is 0xFFFFFFFF, and `minstreth` (the upper 32 bits) is 0. And then you do
```
csrw minstret, zero
```
What value would you expect `minstreth…